After SCL Mohali, Tata's Dholera plant to help startups build prototype chips

After the state-owned Semiconductor Laboratory (SCL) in Mohali, Tata Electronics’ upcoming semiconductor plant in Dholera will provide fabrication support to chip startups for design tape-outs, Union electronics and information technology minister Ashwini Vaishnaw said on Tuesday.

Tape-out is the stage when a chip’s final design is sent to a semiconductor fabrication facility (fab), which then prepares it and produces the first physical prototype chips for testing.

This step is crucial, as many Indian startups have to currently rely on overseas facilities such as Taiwan Semiconductor Manufacturing Company (TSMC) and US-based GlobalFoundries to get even limited samples of chips before actual production can start. This process is costly and also hampers Indian startups’ ability to carry out failure analysis, testing, and identify manufacturing or assembly challenges firsthand.

“The second facility, which will be used for taping-out, will be Tata’s Dholera fab. So the Dholera fab - 28 nanometer (nm) to 90 nm and SCL’s 180 nm. In a sense, close to 75-80% (of the kind of) chips which are manufactured in the world. That entire ecosystem we will be able to build in our country within the next 2-3 years,” Vaishnaw said at an industry event in New Delhi.

The minister met the 24 chip-design firms selected under the Design Linked Incentive (DLI) scheme. The minister said that 14 of these startups have got funding from the venture capitalists to the tune of about ₹430 crore.

Currently, the SCL Mohali facility is being used to support chip-design startups and academia with tape-outs. However, it operates on an outdated 180-nm technology, which limits work on more advanced projects. In November, the government announced a plan to modernise the facility over three years at an investment of ₹4,500 crore.

A government official said on the condition of anonymity that tape-outs of chip designs of academia are largely done at SCL on a multi-project wafer (MPW) basis. A few startups that have reached the stage of tape-outs are usually doing it at TSMC, for which they are getting incentives under the DLI scheme.

An MPW is a shared semiconductor wafer where multiple chip designs from different companies are fabricated together. It is a cost-effective way to manufacture prototype chips by sharing a wafer with multiple designs.

“Tata’s Dholera plant for tape-outs will certainly support the startup ecosystem building products in 28 nm and 40 nm technology. The price points for tape-outs, however, should not be higher than the global rates. Then it will be beneficial,” said Arumugam Govindswamy, managing director of MBit Wireless, a fabless semiconductor company in cellular internet of things (IoT) technology.

According to Govindswamy, the key ask from the government for the next phase of the chip design scheme is higher funding for tape-outs and mass production, besides better market access for selling products.

Separately, Vaishnaw said the government aims to make high-tech small chips of 3-nm nodes by 2032 that are used in products like modern smartphones, and computers. The plan is further to go to 2 nm.

"The level of 2032 is to reach 3 nanometer chips manufacturing and design. Design, of course, we are doing even today. But manufacturing, we should reach 3 nanometer," the minister said, adding that in the coming years, 50% of all the semiconductor design work in the world will be done in India.

Under the second phase of the DLI scheme, the minister said the government will focus on six categories of chips—compute, radio frequency, networking, power, sensor and memory. The minister said the government is targeting to get 50 fabless startups in the next phase of the scheme.

“As we go into 2029, we will have a major capability of manufacturing and designing the chips which are required practically in 70-75% of all applications in our country," the minister said.

As part of the current DLI scheme, startups are entitled to a subsidy of ₹15 crore. There is also a deployment-linked incentives for startups that actually reach the stage of commercial sale of products. However, no startup has been able to claim the deployment-linked incentives of 4-6% of net sales (up to ₹30 crore per application), as no designs have reached the deployment stage.

During the meeting, a few startups urged the government to improve market access for their chip products and increase funding support, as they are entering the mass production phase after tape-out, which entails significant costs.