Centre to spend ₹4,500 crore to modernize SCL Mohali

The Centre will spend ₹4,500 crore over the three years to modernize state-run Semi-Conductor Laboratory (SCL) in Mohali, electronics and IT minister Ashwini Vaishnaw told reporters on the sidelines of the chips-to-startup programme at the facility on Friday.

The Centre plans to fund the investment from the ₹76,000 crore India Semiconductor Mission (ISM 1.0), which was launched in 2021.

“The investment will help in SCL modernization. The plan is to scale up the current production level by 100 times and create new IPs (intellectual property),” he said.

For further expansion of SCL Mohali, Vaishnaw said there is a requirement for 25 acres of land. “We have urged the Punjab government that we need 25 acres of land. The sooner they give, the more it will help in the modernization and expansion of SCL Mohali.”

Mint reported on 10 July that a 26-acre land parcel near the SCL facility in Mohali has emerged as a potential hurdle in the Centre’s plan to modernize the decades-old plant with advanced chip technology.

Owned by the Punjab government, the land was identified by the Centre-run facility over a year ago for its expansion and the addition of new fabrication lines. However, ongoing disputes over the land and a higher price of about ₹700-800 crore demanded by the Punjab government are causing delays to the government’s plans, Mint reported, citing officials aware of the matter.

When asked about the total allocation for SCL from the ISM, Vaishnaw said, “it is a fungible amount. The allocation will be done based on the progress.”

Earlier, the government had talked about earmarking around ₹10,000 crore for SCL's modernization.

Tech upgrade

In February, SCL invited bids to improve the existing 180-nanometre fabrication line. The enhancement of the existing 8-inch fab, which uses the 180-nm technology node, involves the replacement of decades-old equipment.

The focus of the upgradation is also to increase the current production line capacity to 1,500 WSPM (wafer starts per month) from about 700 WSPM, which SCL does presently, showed SCL's documents inviting bids.

A wafer is a thin, flat disk made of silicon (or sometimes other materials) that serves as the base for creating integrated circuits (ICs) or chips.

Mint reported on 1 July that Tata Semiconductor and Israel's Tower Semiconductor have been shortlisted from among nearly a dozen companies to revamp SCL. SCL is yet to select the final bidder.

The 180-nanometer process is an old chipmaking technology. It is still used to make chips for satellites, space and defence systems, medical devices, micro-controllers, power management, etc. In chipmaking, nanometers measure the size of tiny parts like transistors and the spaces between them on a chip. Smaller nanometers mean smaller, faster, and more power-efficient chips.

An 8-inch fab line processes silicon wafers that are 8 inches (200 mm) in diameter. The size of the wafer determines how many semiconductor chips can be made from a single wafer. Today, modern fabrication facilities primarily use larger 12-inch (300 mm) wafers, which allow for more chips per wafer and improved production efficiency.

A modern SCL can play a significant role for India’s deep-tech and semiconductor startups by supporting pilot production, small-volume fabrication, and early-stage prototyping—turning ideas into market-ready products faster, locally, and securely, according to industry executives.

“India has a unique opportunity to position SCL as a strategic national asset,” said Ashok Chandak, president of India Electronics and Semiconductor Association (IESA).

“In the future, after 180 nm (nanometer) setup, modernization should go beyond upgrades—by enabling public–private partnerships that help SCL move from legacy nodes like 180 nm towards advanced nodes such as 65 nm and 28 nm, making it globally competitive,” Chandak said.

In October 2024, SCL also announced its end-to-end support, including fabrication, testing, and packaging, to chip design startups in the country. This means that chip design startups, who are working on the 180-nanometer chip technology for their system on chip (SoC) designs and other products, can now utilize SCL’s manufacturing facility for prototyping and limited-scale manufacturing.

As of now, SCL has received 94 chip designs for fabrication and packaging. The SCL unit has delivered 58 chip designs to startups and academia, including those for manufacturing and packaging. This includes two independent chip design tie-ups.

“SCL Mohali will provide whatever tapeout facility for startups, researchers and academia is required. This is important because no commercial foundry will take up a chip tapeout project of startups,” Vaishnaw said, adding that a consortium involving Centre for Development of Advanced Computing (CDAC), SCL, and organizations like Defence Research and Development Organization (DRDO) will be formed so that chip requirements of the strategic sectors of the country can be identified and fulfilled.

A tapeout in semiconductors is the point when the final, verified design of a chip is officially sent to the semiconductor fabrication plant to begin manufacturing.

As part of the ISM 1.0, the government has approved a total of 10 semiconductor projects with cumulative investments of around ₹1.6 trillion in six states. The government is working on the next leg of incentives, Vaishnaw said.

According to IESA estimates, by 2030, India’s semiconductor demand is projected to reach $103 billion, and 10-15% of this will stem from technologies built on 180nm nodes, such as MEMS (micro-electromechanical systems), CMOS (complementary metal-oxide-semiconductor) image sensors, power semiconductors, analogue, and mixed-signal devices.