Designing Chips Is Getting Harder. These Engineers Say Chatbots and AI Can Help.

QTcore-C1, a chip named and designed by New York University researchers through conversations with ChatGPT.
QTcore-C1, a chip named and designed by New York University researchers through conversations with ChatGPT.


The semiconductor industry is using generative artificial intelligence to accelerate chip design—a process that has become more time-consuming and complex.

The semiconductor industry is using generative artificial intelligence to accelerate chip design—a process that has become more time-consuming and complex, even as the need for advanced chips has grown.

By using the AI systems that power ChatGPT, researchers hope to speed up hardware design—which can take half a year or more for the most complex microchips—to a matter of one month or less, said Siddharth Garg, an institute associate professor of electrical and computer engineering at New York University’s Tandon School of Engineering.

In the past year, chip maker Nvidia, chip design companies Synopsys and Cadence Design Systems, and a host of researchers have developed AI tools designed to speed up engineers’ work by automatically writing hardware code and verifying it, and helping large teams of designers work together by summarizing notes and status updates.

Moves to quicken the pace of design come as supplies of specialized AI chips have been tight since last year’s AI boom kicked off a run on Nvidia’s graphics-processing units, or GPUs.

At the same time, the anticipated end of Moore’s Law, which posits that roughly every two years the number of transistors in a chip doubles, has led companies to explore new chip architectures and the production of more specialized chips. Experts say there aren’t enough U.S. engineers who can design these advanced chips for AI and specific applications like self-driving cars and drones—all of which are growing in demand.

Synopsys’s AI tool, called Copilot and announced last fall, was built with Microsoft using OpenAI’s large-language models and is intended to help engineers collaborate, said Shankar Krishnamoorthy, general manager of the company’s electronic design automation group. Microsoft’s in-house silicon team is using the tool to support its engineering needs, the company said.

The Synopsys AI tool answers questions about how to use the company’s design tools and can create workflow scripts. It can also generate RTL, a form of chip design language that specifies chip architecture, just by having a conversation in plain English.

Owing to their ability to process thousands of tasks at the same time, chips like GPUs require nearly 1,000 people to build, and each must understand how pieces of the design work together as they work to continuously improve them, said Bryan Catanzaro, Nvidia’s vice president of applied deep learning research.

To help, Nvidia developed ChipNeMo, an AI system customized with its own data to perform tasks like respond to questions about GPU architecture and generate chip design language code. The company trained its system on top of models including Meta Platforms’ open-source Llama 2, and the system is designed to be used with existing design automation tools like those from Synopsys.

In the year since Nvidia’s engineers began using ChipNeMo, Catanzaro said they have found it to be most useful in training junior engineers and summarizing notes and status updates for what can be 100 different teams.

Alphabet research lab Google DeepMind developed an AI system to improve logic synthesis, a chip-design phase that involves turning a description of a circuit’s behavior into an actual circuit. Google said those techniques may be used to improve its own custom AI chips, called Tensor Processing Units, or TPUs.

Multiple research efforts at universities including New York University are also under way to determine other ways generative AI can speed up chip design—some of which is funded by companies including Synopsys and mobile-phone chip giant Qualcomm.

A team at NYU’s Tandon School of Engineering designed a chip over the course of about a month by conversing with ChatGPT. The technique, dubbed “Chip Chat," allowed the researchers to automatically write Verilog, a chip design language that describes a chip’s functionality, just by talking with the chatbot, said NYU’s Garg.

But AI-based tools can’t do it all. Right now, they are mostly helpful for things like training younger chip designers, writing hardware languages and reporting bugs, said David Pan, a professor in electrical and computer engineering at the University of Texas at Austin who has advised some of the researchers involved in building such AI tools at companies and universities.

Current tools have other limitations: Human engineers must carefully validate AI-generated output, and there is not yet a solution that can automate the full chip design process, from design to verification, implementation of the design’s transistors and checking the design’s electrical properties.

Synopsys’s Krishnamoorthy estimated that the ability to autonomously create a functional chip using generative AI is about five years away, especially taking AI’s “hallucinations," or misfires, into account.

Write to Belle Lin at

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